Integrated circuits are being produced in smaller and smaller form factors which is leading to a reduction of space available for various additional functionality in these integrated circuits. With reduced space for circuitry for such functionality, all aspects of integrated circuit technology is under pressure to perform faster and with more efficiency. One such area includes automated testing of integrated circuits using common approaches such internal Logic Built-In Self Test circuitry (LBIST) and external Automatic Test Pattern Generator (ATPG) methods.
As integrated circuits become smaller, fewer pins are available for input/output and power distribution. As is now common, a single integrated circuit chip may include only one or two pins suited for external connection to a power supply. Thus, the integrated circuit is designed to perform at optimum levels using the limited power pins. However, as integrated circuit chips are often tested while still in wafer form, Automatic Test Equipment (ATE) may be used to test circuit functionality at various stages of manufacture. A problem that arises with integrated circuits that are highly efficient with respect to distribution of power (e.g., only one or two power pins), is that during ATPG testing, the voltage distribution system in the individual integrated circuit is subject to voltage drops due to transients when various test patterns are clocked simultaneously. That is, with limited pins for power supply in conjunction with simultaneously clocking of internal test circuitry, transient currents drawn at the clock edges often lead to enough of a voltage drop on the power pins that cause erroneous results with regard to the testing. Such erroneous faults due to voltage drops from the testing itself defeat the purpose of integrated circuit testing.